Traditional system-on-chip (SoC) systems utilize large SRAM bulks. The SRAM bulks are used for data buffering, for example, in multiple carrier communication or in data centers. When multiple SRAM bulks are integrated on a SoC, congestion occurs due to a limited number of data-in (DI) and data-out (DO) buses. If the congestion problem cannot be reduced through chip routing/redesign, the area of the SoC must be expanded (to accommodate additional DI/DO buses) and/or the clock frequency lowered, leading to performance degradation and cost increases.
Current SoC systems use distributed SRAM or ring architecture to attempt to address congestion issues. Distributed SRAM makes sharing of SRAM bulks difficult, for example, among each port in a data center. Ring architecture introduces latency increases in the SoC. Both current solutions lead to additional performance degradations in the SoC.